The subject invention generally concerns the field of circuitry for receiving signals from a digital signal bus, and specifically concerns the field of circuitry employing both a differential receiver circuit and a single-ended receiver circuit to capture a differentially driven signal from a digital signal bus.
In modern digital electronic equipment and instruments, it may be necessary for a receiving agent to employ both a differential receiver circuit and a single-ended (i.e., ground-referenced) receiver circuit to capture a differentially driven signal from a digital signal bus. For example, the use of a single-ended receiver circuit is advantageous where the differential bus driver circuit driving the digital bus is a tri-state device, and when and the output of the bus driver is disabled. In such a condition, the input terminals of the differential receiver are held to the same voltage level, which causes its output signal to oscillate. The operation of any edge-triggered circuitry downstream from the differential receiver will be adversely affected by this oscillating output signal. In contrast, the single-ended receiver circuit will not oscillate because its input terminals will not see the same voltage level for any appreciable amount of time.
While use of the single-ended receiver is advantageous in the above-described (i.e. tri-stated) situation, the operation of the differential receiver circuit is superior when data is being driven onto the bus. In such a case, the differential output signal should be used to properly latch data within its specified time window.
Unfortunately, when working with both a differential version and a single-ended version of the same signal, some timing problems can result. These timing problems arise because the single-ended switching point of the signal is unpredictable with respect to the differential switching point, for reasons to be explained in detail below. When the output signals of these two receivers interact in a given system, the above-mentioned timing problems can cause the generation of glitches and other asynchronous anomalies.
What is needed is a circuit that will deterministically locate the output signal of a single-ended receiver with respect to the output signal of a differential receiver, to allow the differential and single-ended output signals to interact in a predictable manner within a given system.
A digital signal receiving circuit employs both a differential receiver circuit and a single-ended receiver circuit to capture a differentially driven signal from a digital signal bus. The output signal of the differential receiver circuit and the output signals of first and second single-ended receiver circuits are coupled to a logic circuit for producing a digital logic output signal exhibiting a substantially stable timing relationship with respect to the output signal of the differential receiver circuit. The logic circuit comprises an AND-OR circuit arrangement for producing a strobe signal exhibiting an active edge that always occurs later in time than an active edge of the differential circuit.